The present invention involves an improvement in the structure and method for making a semiconductor device of the Silicon-on-Insulator (SOI) type having a lateral drift region and conducting field plate. In particular, the present invention sets forth the structure and technique for making an improved structure in a transistor with a lateral drift region where an extension of the gate electrode, or field plate extending laterally over the field oxide, is utilized, in which the gate to drain capacitance is significantly reduced by maintaining the entire field plate, but reducing the lateral length of the field plate which is connected to the gate.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, xe2x80x9conxe2x80x9d resistance, manufacturing simplicity and reliability, and switching cycle times and energy dissipation. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational drawbacks and fabricational complexities.
Improvements over the basic SOI structure, in which increased breakdown voltages are achieved by providing a linear doping profile in the drift region, are shown in related U.S. Pat. Nos. 5,246,870 and 5,412,241, both commonly assigned with the instant application and incorporated herein by reference. In these SOI devices, the drift region between the channel, or body, and the drain in the lateral MOS structure is provided with various features, such as a thinned portion and a linear lateral doping density profile, which result in substantially increased breakdown voltage characteristics. Additionally, a top field plate is provided over a field oxide of essentially constant thickness to permit twice the conducting charge to be placed in the drift region, thereby reducing conduction losses without reducing breakdown voltage. However, to maintain high breakdown voltage, the total amount of conduction charge near the source side of the drift region must be kept very small, thereby leading to a bottleneck for current flow and preventing optimum reduction in conduction losses.
A further improvement to the basic SOI structure is shown in U.S. Pat. No. 5,648,671, which shows a lateral thin-film SOI device with a linearly-graded field oxide region and a linear doping profile, features which serve to reduce conduction losses without reducing breakdown voltage. A further improvement to that structure is shown in U.S. Pat. No. 5,969,387, commonly assigned with the instant application, and co-invented by two of the present inventors, which is also incorporated herein by reference. The improvement of that patent, whose object is to provide advanced enhanced device performance, discloses a portion of the top oxide layer being increased in thickness in a substantially continuous manner, while a portion of a lateral drift region beneath the top oxide layer, or field oxide layer, being decreased in thickness in a substantially continuous manner, both over a distance which is at least about a a factor of 5 greater than the maximum thickness of the thin semiconductor film.
Yet another improved high-voltage thin-film device is disclosed in U.S. Pat. No. 6,028,337, commonly assigned with the instant application, and co-invented by two of the present inventors, and is incorporated herein by reference as well. This latter improvement provided additional structure within the device for depleting a portion of the drift region adjacent the body region in a lateral direction during operation, in addition to the conventional depletion in the vertical direction which normally occurs in devices of this general type. Theses prior art devices are mentioned by way of example, and there are obviously many other versions of these devices with other improvements and enhancements to the basic SOI LDMOS structure in the prior art.
While disclosing numerous important improvements to the basic SOI LDMOS device, none of the prior art devices deal with the problem of the increased gate to drain capacitance which is a by-product of the top field plate (electrically connected to the gate electrode, and sometimes simply an extension of it) which laterally extends over the field oxide, which itself laterally extends over the drift channel, such top field plate being first introduced in U.S. Pat. Nos. 5,246,870 and 5,412,241, and now commonly part of the standard SOI LDMOS structure. The problem of the resultant increased gate to drain capacitance will be more further described below, and is the concern of the method and structure of the present invention. Its existence directly results in increased gate to drain capacitance, and as a result, increased energy dissipation during transistor switching, and thus energy inefficiency.
Accordingly, it would be desirable to have a transistor device structure capable of high performance in a high-voltage, high current environment, in which operating parameters, in particular lower gate to drain capacitance, and the resulting decreased energy dissipation during switching, are further optimized.
The present invention seeks to improve upon the above described structures of the prior art by maintaining the benefits of the top field plate, yet, at the same time, reducing the gate to drain capacitance of the device, and thus reducing the energy dissipation during switching. This is effected by a reduction in the overlap of the gate electrode, and the electrically connected field plate, with the drift region of the device. This is accomplished by maintaining the entire top field plate as in the prior art, while severing it from the gate electrode and connecting those portions back to the source, thereby decreasing the gate to drain resistance. Even more benefit is realized by severing the polysilicon gate electrode and connecting the laterally drainward portion to the field plate and leaving only a small sourceward portion of the polysilicon connected to the gate.
In one embodiment, where the top field plate comprises an extended polysilicon gate contact extending partially over the drift region and a metal field plate attached to the gate contact laterally protruding over more of the drift region, the metal field plate attached to the polysilicon gate electrode is severed therefrom and connected back to the source contact. This restricts the gate overlap of the drift region to just the extended polysilicon.
In another, and preferred, embodiment, as summarily described above, the extended polysilicon gate contact itself is severed into two portions. One smaller portion, at the source side of the device, remains connected to the gate electrode and extends over a small portion of the field oxide, and the other larger portion, being connected to the metal field plate, is connected back to the source, restricting the overlap of the gate with the drift region, and thus reducing the gate to drain capacitance, even further.
By utilizing the method of the preferred embodiment, significant reduction in energy dissipation during switching is achieved. The effect increases with the drain voltage and the drain current.